National ICT R&D Fund

Technical R&D Projects

Funded Projects

Design and Verification of Low-Power, High-Speed IP Suite for Universal Serial Bus (USB 3.0)

Principal Investigator:
School of Electrical Engineering and Computer Science National University of Science & Technology (NUST) www.niit.edu.pk
Project Directors:
Dr. Nazar Abbas Saqib	nazar@niit.edu.pk
Mr. Jahangir Hashmi	jahangir@whizzsilicon.com
Project Details:
Start Date: March, 2009	Duration: 24 months
Project Cost: PKR 35.48 million	Project Funding: PKR 35.48 million
Project Status: In progress.
Technical Progress Reports Submitted: Project Commencement Report, Q1, Q2, Q3, Q4 and Q5 reports. Pending Reports: None. Deliverables Submitted: 1: Training material for the team 2: Micro Architecture Pending Deliverables: None.
Financial Audit Reports Submitted: Q1-Q5 financial reports.
Project URL: http://asicfpga.seecs.nust.edu.pk/pages/introduction.html
Detailed proposal is available here.

Executive Summary:

Universal Serial Bus (USB) is used to connect all sorts of devices and is the most successful computer standard in history with billions of units shipped. Current solutions based on USB 2.0, support transfer rates up to 480 Mb/s but that rate will soon increase tenfold to 4.8Gb/s with the introduction of USB 3.0 enabled products.

Over the past several years, there has been a shift in how consumers access and use audio/video media content. Wide use of HD Camcorders, HDTVs, Blue-Ray Disks, and other devices has elevated the need for high-speed data transfer. The early Super Speed products will be based on discrete USB 3.0 transceiver/controllers, and its broad deployment will likely take place by 2010. To bring the cost-effective solution to market, the USB 3.0 functionality would have to be integrated into the devices. This provides new opportunities for producing world-class USB 3.0 IP for SoC/ASIC integration. Most ASICs / SoCs rely on third party IPs for large parts of the total chip functionality. The availability of proven IPs has been pivotal in helping companies keep up with the new standards.

This project plans to develop a suite of low power, configurable and high speed USB 3.0 IP cores including IPs for USB 3.0 host controller, USB 3.0 device controller and USB 3.0 support functions to meet the needs of this "poised-to-explode" market.

The project will research design and verification techniques for developing high speed IP cores for Speed critical devices and low power optimization techniques to look for their applicability to the proposed design. It will develop architecture and the micro-architectures for the Host and Device controllers and test plan for verification of controllers.

The key benefits of this project are:

USB is the most popular standard in the computing world. The Super Speed USB is expected to be the interface choice for most high-speed data transfer needs. Most of the semiconductor and systems companies world-wide will transition their products to Super Speed USB and could use the proposed IP.
The project will produce algorithms/architecture for the USB 3.0 controllers.
The architecture and the micro-architecture developed for this project will result in development of commercial IP. It will serve as bases for creating several other products.